Silicon carbide (SiC) is a wide-bandgap semiconductor having a wide forbidden band of from 2.2 eV to 3.3 eV, and due to excellent physical and chemical characteristics thereof, research and development of SiC as an environmentally-resistant semiconductor material have been carried out. Particularly in recent years, SiC is drawing attention as a material for a short-wavelength optical device configured to emit blue light to ultraviolet light, a high-frequency electronic device, and a high-breakdown-voltage and high-output electronic device, and the research and development of SiC are becoming active. However, SiC is considered to be difficult to produce a good-quality single crystal having a large diameter, which has hitherto prevented a SiC device from being put into practical use.
Hitherto, on a scale of a research laboratory, for example, a sublimation-recrystallization method (Lely method) has been used to obtain a SiC single crystal having a size capable of manufacturing a semiconductor element. However, according to this method, the area of a single crystal to be obtained is small, and it is not easy to control the dimensions, shape, crystal polymorph (polytype), and concentration of impurity carriers. Meanwhile, chemical vapor deposition (CVD) has also been used to grow a cubic SiC single crystal through heteroepitaxial growth on a foreign substrate of silicon (Si) or the like. In this method, a single crystal having a large area is obtained, but only a SiC single crystal containing a large number of defects (≈107/cm2) can be grown due to the lattice mismatch between SiC and Si of about 20%, with the result that a high-quality SiC single crystal has not been obtained.
In order to solve the above-mentioned problems, there has been proposed a modified Lely method involving performing sublimation-recrystallization through use of a SiC single crystal wafer as a seed crystal (see Non Patent Literature 1). When the modified Lely method is used, a SiC single crystal can be grown while controlling the crystal polymorph (6H-type, 4H-type, 15R-type, etc.), shape, carrier type, and concentration of the SiC single crystal. It should be noted that, among 200 or more crystal polymorphs (polytypes) of SiC, a 4H polytype is considered to be most excellent in terms of the productivity of a crystal and the performance of an electronic device, and hence most of SiC single crystals that have been commercially produced are of the 4H-type. Further, a single crystal ingot is grown so as to have n-type conductivity in most cases because nitrogen is easy to handle as a dopant. It should be noted that a crystal having a high resistivity, which is substantially free of a dopant element, has also been produced in the application to communication devices.
In order to use a SiC single crystal ingot as a SiC wafer for manufacturing a semiconductor device, it is necessary to process the SiC single crystal ingot produced by a method such as the above-mentioned modified Lely method into a wafer shape through the process mainly involving cutting and polishing. That is, a SiC single crystal wafer having a thin plate shape, which is cut by a method such as a wire saw so that a desired crystal surface is exposed, is subjected to mirror polishing processing through a polishing process substantially similar to a method that is generally performed in other semiconductor materials such as silicon, and various electronic devices are manufactured through use of the SiC single crystal wafer thus produced.
Currently, a SiC single crystal wafer having a diameter of from 51 mm (2 inches) to 100 mm is cut out from a SiC single crystal produced by the modified Lely method and is used for manufacturing devices in the fields of power electronics and the like. Further, the success of the development of a wafer having a diameter of 150 mm has also been reported (see Non Patent Literature 2), and thus the full-scale commercial manufacturing of devices using a wafer having a diameter of 100 mm or 150 mm is being realized.
Incidentally, in general, the flatness of a wafer expressed as so-called “warpage” is considered to be very important in terms of a device step. This is because, in a wafer having poor flatness, that is, having large warpage, a part within a wafer surface becomes out of focus in an exposure process (lithograph process), with the result that a clear mask image is not formed. Needless to say, the out-of-focus phenomenon has a larger effect as a circuit is finer.
If the warpage of a product wafer after polishing can be predicted before the completion of the polishing step, steps can be selected, for example, as follows: a wafer is polished after selecting an application based on the value of warpage (polishing specifications vary depending on the kind of a device inmost cases); a wafer that has been found to be unable to be formed into a product based on the magnitude of warpage is not subjected to the polishing step; or a wafer is subjected to annealing treatment at high temperature and classified into the application in which a dislocation density is allowed. With this, a wafer can be efficiently formed into a product, and simultaneously, the waste of the expensive polishing step is cut to decrease cost. Therefore, the prediction of warpage is very important from the industrial viewpoint.
The warpage of a SiC single crystal wafer is generally determined based on the following three factors: (i) internal stress of a crystal; (ii) accuracy of cutting and processing residual strain on front and back surfaces of a wafer; and (iii) removal of residual strain on front and back surfaces in a polishing step and the process thereof. The factor (i) is determined by the conditions of crystal growth and the heat treatment to be conducted thereafter. The factor (ii) is determined by the accuracy of the motions of a wire and a blade, and the processing strain applied to a surface in a cutting step. A change in warpage caused by the factor (iii) is generally called a Twyman's effect, and in this case, a wafer is warped so that a surface having large strain is projected. That is, the warpage of a wafer reaches the warpage of a product wafer after the completion of final polishing through different courses during the process, depending on the growth conditions, the accuracy of the cutting step and the polishing step, and the contents thereof. As a result, the value of the magnitude of the warpage of the wafer in the polishing step is not matched with that of the magnitude of the warpage of the wafer after the completion of final polishing, and in addition, the tendency of a change in warpage in the steps is not uniform. Thus, hitherto, there has been no technology of predicting the warpage of a wafer before the completion of polishing.
Meanwhile, as means for reducing the warpage amount of a wafer, for example, the following methods have been considered. In Patent Literature 1, there has been reported a technology involving subjecting a wafer cut out from a SiC single crystal ingot to annealing treatment at a temperature of 1,300° C. or more and 2,000° C. or less so as to remove a processing residual stress caused by grinding and cutting of the ingot, thereby reducing the warpage amount of a wafer. Further, in Patent Literature 2, there has been reported a technology involving annealing an ingot or a wafer of a SiC single crystal at a temperature of more than 2,000° C. and 2,800° C. or less in an atmosphere of noncorrosive gas containing carbon and hydrogen or an atmosphere in which argon and helium are mixed with the noncorrosive gas, so as to relieve the internal stress of the ingot or the wafer, thereby preventing cracking and cracks during processing of the ingot or in a device process of the wafer. Further, in Patent Literature 3, there has been reported a technology involving subjecting a wafer cut out from a SiC single crystal ingot to heat treatment at 800° C. or more and 2,400° C. while pressurizing the wafer at 10 MPa or more and 0.5 MPa or less, thereby setting the radius of curvature of the wafer to 35 m or more. In Patent Literature 4, there has been proposed a polishing and surface-finishing technology of reducing warpage, and there has also been disclosed a technology involving removing a processing altered layer formed by mechanical flattening processing or cutting processing by vapor-phase etching, thereby eliminating the warpage of a SiC wafer.
Patent Literature 1, 2, or 3 is considered to be effective for relieving the internal stress of a grown crystal. However, when atoms are rearranged by applying a thermal load of more than 2,000° C. from outside to a SiC single crystal, a new crystal defect may be caused. An increase in dislocation density of a crystal after annealing in Examples of Patent Literature 3 indicates the above-mentioned phenomenon. Further, what can be commonly said about Patent Literature 4 as well as Patent Literatures 1, 2, and 3 is that those technologies are not for predicting the warpage of a wafer after polishing. In the industrial-scale production, it is impossible to set the warpage of all wafers to a value close to 0, and even when a production technology of reducing the warpage is available, the evaluation technology of predicting the warpage is still important.